Senior Engineer, Mixed-signal IP Verification

Job Reference BBBH99095_1619592939

Salary S$5000 - S$6500 per month + VB

Responsibilities

• Perform functional verification of mixed-signal IP modules or subsystems
• Work with IC Design team for pre-silicon verification (chip level verification) and post silicon validation
• Ensure highest quality through fault grading and analyse functional test patterns
• Work closely with Product Engineers during NPI phase and address any post-production issues e.g. Yield, Design or Quality

Requirements

• Bachelors/ Master's in Electrical/ Electronic and Computer Engineering
• Minimum 3 years of experience in RTL design and HW functional verification closure techniques
• Experience in writing synthesizable RTL; Verilog/ SystemVerilog
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc.

Teh Hui Tian, Zoe EA License No. 02C3423 Personnel Registration No. R2089915